1. Field of the Invention
The present invention relates to a regulator and in particular to a low dropout regulator having an over-current protection circuit capable of preventing an overcurrent from flowing through the regulator.
2. Description of the Related Art
A regulator converts an unstable power supply voltage into a stable power supply voltage. A low dropout (LDO) regulator has a low input-to-output voltage difference between an input terminal where an unstable power supply voltage is inputted and an output terminal where a stable power supply voltage is outputted. “Dropout voltage” refers to the input-to-output voltage difference at which the regulator ceases to regulate against further reductions in input voltage. Ideally, the dropout voltage should be as low as possible, to allow the input voltage to be relatively low and still maintain regulation. This assures that the input-to-output voltage difference is low, minimizing power dissipation and maximizing efficiency.
FIG. 1 is a circuit diagram illustrating a conventional LDO regulator. Referring to FIG. 1, the typical LDO regulator circuit includes a reference voltage generator 200, an error amplifier 100, a pass transistor MP1, and resistors R1 and R2.
An unregulated power supply voltage VIN is applied to a source terminal of the pass transistor MP1. The current flowing through the pass transistor MP1 flows through the resistors R1 and R2 and then flows to ground GND. A regulated power supply voltage VOUT is outputted to an output terminal coupled to a drain terminal of the pass transistor MP1.
A reference voltage Vref outputted from the reference voltage generator 200 is applied to the inverted input terminal of the error amplifier 100, and a voltage Vf across the resistor R2 is applied into the non-inverted input terminal of the error amplifier 100, as shown in FIGS. 1 and 2. An output signal VEO of the error amplifier 100 is applied into a gate of the pass transistor MP1. The current flowing through the pass transistor MP1 is sensed by the resistor R2 and converted into a voltage signal Vf.
The voltage signal Vf is inputted into the non-inverted input terminal of the error amplifier 100 and is compared to the reference voltage Vref. The output voltage VOUT may be represented as VOUT=Vref×((1+Rf)/Rf). The reference voltage Vref is a stable voltage and, therefore, the output voltage VOUT is a stable voltage.
Generally, the conventional LDO regulator includes a protection circuit such as an over-current protection circuit so as to protect the circuit during abnormal operating conditions. For example, FIG. 2 is a circuit diagram illustrating a conventional low dropout regulator for providing over-current protection. Referring to FIG. 2, the LDO regulator for providing over-current protection includes a protection circuit composed of a resistor RS1 and a PMOS transistor MP2, in addition to the circuit components illustrated in FIG. 1.
During abnormal operating conditions, when an unregulated power supply voltage VIN increases, the current flowing through the pass transistor MP1 overly increases and a voltage VRS1 across the resistor RS1 increases. When the voltage VRS1 across the resistor RS1 is larger than a threshold voltage of the PMOS transistor MP2, the PMOS transistor is turned on. An electric potential of a gate of the pass transistor MP1 becomes high and a current flowing through the pass transistor MP1 decreases. Accordingly, although the unregulated power supply voltage VIN overly increases, the pass transistor MP1 may be protected using the protection circuit composed of the resistor RS1 and the PMOS transistor MP2.
However, when the load current is about 100 mA, the voltage dropout between the input and output terminals of the LDO regulator is about 100 mV to about 200 mV. This means that the resistor RS1 needs to have a resistance value below 1 ohm. Implementing the resistor RS1 having a resistance below 1 ohm occupies a large area in a semiconductor chip.